PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 17

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.0
There are two memory blocks in each of these
PICmicro
memory have separate buses so that concurrent
access can occur and is detailed in this section. The
program memory can be read internally by user code
(see Section 3.0 “Reading Program Memory”).
Additional information on device memory may be found
in the “PICmicro
Manual” (DS33023).
2.1
The PIC16F7X7 devices have a 13-bit program counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F767/777 devices have
8K words of Flash program memory and the
PIC16F737/747 devices have 4K words. The program
memory maps for PIC16F7X7 devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
 2004 Microchip Technology Inc.
MEMORY ORGANIZATION
Program Memory Organization
®
MCUs. The program memory and data
®
Mid-Range MCU Family Reference
Program
On-Chip
Memory
PROGRAM MEMORY MAPS AND STACKS FOR PIC16F7X7 DEVICES
CALL, RETURN
RETFIE, RETLW
Interrupt Vector
Stack Level 8
Stack Level 2
Reset Vector
Stack Level 1
PC<12:0>
Page 0
Page 1
Page 3
Page2
13
0000h
0004h
0005h
0FFFh
1000h
17FFh
1800h
1FFFh
07FFh
0800h
2.2
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (Status<6>) and
RP0 (Status<5>) are the bank select bits:
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register (FSR).
Memory available on PIC16F767
and PIC16F777. The memory
wraps to 000h through 0FFFh on
the PIC16F737 and PIC16F747.
Memory available on all
PIC16F7X7.
Data Memory Organization
RP1:RP0
GENERAL PURPOSE
REGISTER FILE
00
01
10
11
PIC16F7X7
DS30498C-page 15
Bank
0
1
2
3