ATMEGA168PA-PU Atmel, ATMEGA168PA-PU Datasheet - Page 82

MCU, 8BIT, AVR, 16K FLASH, 28PDIP

ATMEGA168PA-PU

Manufacturer Part Number
ATMEGA168PA-PU
Description
MCU, 8BIT, AVR, 16K FLASH, 28PDIP
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA168PA-PU

Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
No.
RoHS Compliant
Core Size
8bit
Program Memory Size
16KB
Oscillator Type
External, Internal
Rohs Compliant
Yes

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA168PA-PU
Manufacturer:
TI
Quantity:
1 240
8271C–AVR–08/10
Table 13-2
ure 13-5 on page 81
generated internally in the modules having the alternate function.
Table 13-2.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
summarizes the function of the overriding signals. The pin and port indexes from
Generic Description of Overriding Signals for Alternate Functions
Full Name
Pull-up Override
Enable
Pull-up Override
Value
Data Direction
Override Enable
Data Direction
Override Value
Port Value
Override Enable
Port Value
Override Value
Port Toggle
Override Enable
Digital Input
Enable Override
Enable
Digital Input
Enable Override
Value
Digital Input
Analog
Input/Output
are not shown in the succeeding tables. The overriding signals are
Description
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn,
and PUD Register bits.
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable
is determined by MCU state (Normal mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the Schmitt Trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
Fig-
82

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