ATMEGA168PA-PU Atmel, ATMEGA168PA-PU Datasheet - Page 77

• Manufacturer Part Number: ATMEGA168PA-PU
• Description: MCU, 8BIT, AVR, 16K FLASH, 28PDIP
• Manufacturer: Atmel

Specifications of ATMEGA168PA-PU

• Controller Family/series: Atmega
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No.: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 16KB
• Oscillator Type: External, Internal
• Rohs Compliant: Yes

13.2
13.2.1
8271C–AVR–08/10
Ports as General Digital I/O
Configuring the Pin
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 13-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
93, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
(1)
SLEEP
SYNCHRONIZER
WDx:
RDx:
WRx:
RRx:
RPx:
D
L
WPx:
Q
Q
D
PINxn
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
Figure 13-2
PUD
WDx
RDx
RPx
clk
1
0
WRx
I/O
WPx
shows a func-
”Register
I/O
,
77