ATMEGA168PA-PU Atmel, ATMEGA168PA-PU Datasheet - Page 157

MCU, 8BIT, AVR, 16K FLASH, 28PDIP

ATMEGA168PA-PU

Manufacturer Part Number
ATMEGA168PA-PU
Description
MCU, 8BIT, AVR, 16K FLASH, 28PDIP
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA168PA-PU

Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
No.
RoHS Compliant
Core Size
8bit
Program Memory Size
16KB
Oscillator Type
External, Internal
Rohs Compliant
Yes

Available stocks

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Manufacturer
Quantity
Price
Part Number:
ATMEGA168PA-PU
Manufacturer:
TI
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1 240
17.10 Timer/Counter Prescaler
8271C–AVR–08/10
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous
timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least
one before the processor can read the timer value causing the setting of the Interrupt Flag. The
Output Compare pin is changed on the timer clock and is not synchronized to the processor
clock.
Figure 17-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
system I/O clock clk
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP.
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock
(clk
until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-
save mode is essentially unpredictable, as it depends on the wake-up time. The recommended
procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT2.
I/O
PSRASY
) again becomes active, TCNT2 will read as the previous value (before entering sleep)
TOSC1
clk
CS20
CS21
CS22
AS2
I/O
IO
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clk
T2S
Clear
TIMER/COUNTER2 CLOCK SOURCE
T2S
0
. clk
10-BIT T/C PRESCALER
T2S
clk
T2
is by default connected to the main
157

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