ATMEGA168PA-PU Atmel, ATMEGA168PA-PU Datasheet - Page 292

MCU, 8BIT, AVR, 16K FLASH, 28PDIP

ATMEGA168PA-PU

Manufacturer Part Number
ATMEGA168PA-PU
Description
MCU, 8BIT, AVR, 16K FLASH, 28PDIP
Manufacturer
Atmel
Datasheet

Specifications of ATMEGA168PA-PU

Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
20MHz
No.
RoHS Compliant
Core Size
8bit
Program Memory Size
16KB
Oscillator Type
External, Internal
Rohs Compliant
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA168PA-PU
Manufacturer:
TI
Quantity:
1 240
26.8.15
In
Table 26-10. Boot Size Configuration, ATmega168A/168PA
Table 26-11. Read-While-Write Limit, ATmega168A/168PA
For details about these two section, see
Write Section” on page 280
Table 26-12. Explanation of Different Variables used in
Note:
8271C–AVR–08/10
BOOTSZ1
Section
Read-While-Write section (RWW)
No Read-While-Write section (NRWW)
Variable
PCMSB
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
Table 26-10
1
1
0
0
1. Z15:Z14: always ignored
ATmega168A and ATmega168PA Boot Loader Parameters
Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See
Programming.
BOOTSZ0
ATmega168A/168PA
through
”Addressing the Flash During Self-Programming” on page 284
1
0
1
0
Table
Boot
Size
128 words
256 words
512 words
1024 words
PC[12:6]
Note:
PC[5:0]
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
12
5
26-12, the parameters used in the description of the self programming are given.
The different BOOTSZ Fuse configurations are shown in
Pages
16
2
4
8
”NRWW – No Read-While-Write Section” on page 280
Corresponding
Application
Flash
Section
0x0000 - 0x1F7F
0x0000 - 0x1EFF
0x0000 - 0x1DFF
0x0000 - 0x1BFF
Z-value
Z13:Z7
Z6:Z1
Z13
Z6
(1)
Figure 26-3
Boot
Loader
Flash
Section
0x1F80 - 0x1FFF
0x1F00 - 0x1FFF
0x1E00 - 0x1FFF
0x1C00 - 0x1FFF
Description
Most significant bit in the Program Counter. (The Program Counter
is 13 bits PC[12:0])
Most significant bit which is used to address the words within
one page (64 words in a page requires 6 bits PC [5:0])
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used,
the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not
used, the ZPAGEMSB equals PAGEMSB + 1.
Program counter page address: Page select, for page erase and
page write
Program counter word address: Word select, for filling temporary
buffer (must be zero during page write operation)
Pages
112
16
and the Mapping to the Z-pointer,
for details about the use of Z-pointer during Self-
End
Application
Section
0x1F7F
0x1EFF
0x1DFF
0x1BFF
Address
0x0000 - 0x1BFF
0x1C00 - 0x1FFF
Figure 26-2 on page
Boot Reset Address (Start Boot
Loader Section)
0x1F80
0x1F00
0x1E00
0x1C00
and
”RWW – Read-While-
282.
292

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