WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 88

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.4.1.1
5.4.4.2
Note:
5.4.4.2.1
5.4.4.2.2
88
When entering the D0u state, the 82574 disables all wake ups and asserts a reset to
the PHY while the NVM is being read. If the APM Mode bit in the NVM's Initialization
Control Word 2 is set, then APM wake up is enabled.
Entry into D0u state
D0u is reached from either the Dr state (on assertion of Internal PwrGd) or the D3hot
state (by configuration software writing a value of 00b to the Power State field of the
PCI-PM registers).
Asserting Internal PwrGd means that the entire state of the device is cleared, other
than sticky bits. The state is loaded from the NVM, followed by establishment of the
PCIe link. Once this is done, configuration software can access the device.
On a transition from the D3 to D0u state, the 82574’s PCI configuration space is not
reset. Per the PCI Power Management Specification (revision 1.1, Section 5.4),
software “will need to perform a full re-initialization of the function including its PCI
Configuration Space.”
D0active State
Once memory space is enabled, all internal clocks are activated and the 82574 enters
an active state. It can transmit and receive packets if properly configured by the
software device driver. The PHY is enabled or re-enabled by the software device driver
to operate / auto-negotiate to full-line speed/power if not already operating at full
capability. Any APM Wakeup previously active remains active. The software device
driver can deactivate APM Wakeup by writing to the WUC register, or activate other
wake-up filters by writing to the Wake Up Filter Control (WUFC) register.
Fields that are auto-loaded from the NVM, like WUC.APME, should be configured
through an NVM setting, because D3 to D0 power state transition causes NVM auto-
read to reload those bits from the NVM.
Entry to D0a State
D0a is entered from the D0u state by writing a 1b to the Memory Access Enable or the
I/O Access Enable bit in the PCI Command register. The DMA, MAC, and PHY are
enabled. Manageability is also enabled if configured from the NVM.
D3 State (=PCI-PM D3hot)
When the system writes a 11b to the Power State field in the PMCSR, the 82574
transitions to D3. Any wake-up filter settings that were enabled before entering this
reset state are maintained. Upon transition to D3 state, the 82574 clears the Memory
Access Enable and I/O Access Enable bits of the PCI Command register, which disables
memory access decode. In D3, the 82574 only responds to PCI configuration accesses
and does not generate master cycles.
A D3 state is followed by either a D0u state (in preparation for a D0a state) or by a
transition to Dr state (PCI-PM D3cold state). To transition back to D0u, the system
writes a 00b to the Power State field of the PMCSR. Transition to Dr state is through
PE_RST_N assertion.
82574 GbE Controller—Power Management and Delivery