WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 141

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.1.6
Note:
7.1.7
7.1.7.1
Receive Descriptor Fetching
The fetching algorithm attempts to make the best use of PCIe bandwidth by fetching a
cache-line (or more) descriptor with each burst. The following paragraphs briefly
describe the descriptor fetch algorithm and the software control provided.
When the on-chip buffer is empty, a fetch happens as soon as any descriptors are made
available (host writes to the tail pointer). When the on-chip buffer is nearly empty
(RXDCTL.PTHRESH), a prefetch is performed each time enough valid descriptors
(RXDCTL.HTHRESH) are available in host memory and no other PCIe activity of greater
priority is pending (descriptor fetches and write backs or packet data transfers).
When the number of descriptors in host memory is greater than the available on-chip
descriptor storage, the chip might elect to perform a fetch that is not a multiple of
cache line size. The hardware performs this non-aligned fetch if doing so results in the
next descriptor fetch being aligned on a cache line boundary. This enables the
descriptor fetch mechanism to be most efficient in the cases where it has fallen behind
software.
The 82574L NEVER fetches descriptors beyond the descriptor tail pointer.
Receive Descriptor Write Back
Processors have cache line sizes that are larger than the receive descriptor size (16
bytes). Consequently, writing back descriptor information for each received packet can
cause expensive partial cache line updates. Two mechanisms minimize the occurrence
of partial line write backs:
The following sections explain these mechanisms.
Receive Descriptor Packing
To maximize memory efficiency, receive descriptors are packed together and written as
a cache line whenever possible. Descriptors accumulate and are opportunistically
written out in cache line-oriented chunks. Used descriptors are also explicitly written
out under the following scenarios:
When the number of descriptors specified by RXDCTL.WTHRESH have been used, they
are written back, regardless of cache line alignment. It is therefore recommended that
WTHRESH be a multiple of cache line size. When a receive timer (RADV or RDTR)
expires, all used descriptors are forced to be written back prior to initiating the
interrupt, for consistency. Software might explicitly flush accumulated descriptors by
writing the RDTR register with the high order bit (FPD) set.
• Receive descriptor packing
• Null descriptor padding
• RXDCTL.WTHRESH descriptors have been used (the specified maximum threshold
• The last descriptors of the allocated descriptor ring have been used (to enable
• A receive timer expires (RADV or RDTR)
• Explicit software flush (RDTR.FPD)
of unwritten used descriptors has been reached)
hardware to re-align to the descriptor ring start)
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