WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 173

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.2.11.4
7.2.11.5
Table 43.
7.2.11.6
Note:
Note:
Status - STA
The status field is written back to host memory in cases where the RS bit is set in the
command field. The DD bit indicates that the descriptor is done after the descriptor has
been processed.
Rsv (bit 3:1) - Reserved
DD (bit 0) - Descriptor done
Extended Command
The extended command field (TDESC.ExtCMD) provides additional control options.
Table 43
Transmit Extended Command (TDESC.ExtCMD) Layout
TimeStamp (bit 0) - Indication to stamp the transmitted packet time for TimeSync.
Packet Options - POPTS
The POPTS field provides a number of options, which control the handling of this
packet. This field is relevant only on the first data descriptor of a packet or
segmentation context.
Rsv (bits 7:2) - Reserved
TXSM (bit 1) - Insert TCP/UDP checksum
IXSM (bit 0) - Insert IP checksum
IXSM and TXSM are used to control insertion of the IP and TCP/UDP checksums,
respectively. If the corresponding bit is not set, whatever value software has placed
into the checksum field of the packet data is placed on the wire.
For proper values of the IP and TCP checksum, software must set the IXSM and TXSM
when using the transmit segmentation.
Software should not set this field for IPv6 packets.
7
3
3
lists the bit definitions for the DCMD field.
Rsv
Reserved
Rsv
2
2
2
1
1
TXSM
1
TimeStamp
IXSM
0
DD
0
0
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