WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 486

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

486
External Power
supply
(Option C)
Integrated Power
Supply
(Option D)
Section
Derive all three power supplies from auxiliary
power supplies.
If the 1.05 V dc and 1.9 V dc rails are
externally supplied, ensure that CTRL10 and
CTRL19 are tied to ground through a 3.3 K
resistor. Alternatively, they could be left
floating.
Connect DIS_REG10 to the 3.3 V dc supply
with a 1 K resister.
It is recommended that the 1.9 V dc supply be
tunable with a resistor option.
The 3.3 V dc rail should have at least 25 F of
capacitance.
The 1.05 V dc and 1.9 V dc rails should have
at least 20 F of capacitance.
Place these to minimize the inductance from
each power pin to the nearest decoupling
capacitor.
All voltages should ramp to within their control
bands in 100 ms or less. Voltages must ramp
in sequence (3.3 V dc ramps first, 1.9 V dc
ramps second, 1.05 V dc ramps last). The
voltage rise must be monotonic. The minimum
rise time on the 3.3 V dc power is 1 ms.
Provide a 3.3 V dc and 1.9 V dc supply. Derive
power supplies from auxiliary power supplies.
Ensure that CTRL10 and CTRL19 are tied to
ground through a 3.3 K resistor.
Alternatively, they could be left floating.
Connect DIS_REG10 to ground.
The 3.3 V dc rail should have at least 25 F of
capacitance.
The 1.05 V dc and 1.9 V dc rails should have
20- 40 F of capacitance.
Place these to minimize the inductance from
each power pin to the nearest decoupling
capacitor.
Check Items
82574 GbE Controller—Board Layout and Schematic Checklists
Auxiliary power is necessary to support wake up from
power down states.
Pull-down resistors do not need to be exactly 3.3 K;
however, they must be greater than 1 K.
Disable internal 1.05 V dc regulator.
Tuning the 1.9 V dc supply might be required to
optimize MDI performance.
Place decoupling and bulk capacitors close to 82574,
with some along every side, using short, wide traces
and large vias. If power is distributed on traces, bulk
capacitors should be used at both ends. If power is
distributed on cards, bulk capacitors should be used at
the connector.
The 82574 has a power on reset circuit that requires a
1-100 ms ramp time. The rise must be montonic to so
the power on reset triggers only once.
The sequence is required protect the ESD diodes
connected to the power supplies from being forward
biased
Auxiliary power is necessary to support wake up from
power down states.
Pull-down resistors do not need to be exactly 3.3 K;
however, they must be greater than 1 K.
Enable internal 1.05 V dc regulator.
Place decoupling and bulk capacitors close to 82574,
with some along every side, using short, wide traces
and large vias. If power is distributed on traces, bulk
capacitors should be used at both ends. If power is
distributed on cards, bulk capacitors should be used at
the connector.
Remarks