WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 450

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.5.5
13.5.5.6
Note:
13.5.5.7
450
Signal Termination and Coupling
The 82574 has internal termination on the MDI signals. External resistors are not
needed. Adding pads for external resistors can degrade signal integrity.
Signal Trace Geometry for 1000 BASE-T Designs
The key factors in controlling trace EMI radiation are the trace length and the ratio of
trace-width to trace-height above the reference plane. To minimize trace inductance,
high-speed signals and signal layers that are close to a reference or power plane should
be as short and wide as practical. Ideally, this trace width to height above the ground
plane ratio is between 1:1 and 3:1. To maintain trace impedance, the width of the trace
should be modified when changing from one board layer to another if the two layers are
not equidistant from the neighboring planes.
Each pair of signal should have a differential impedance of 100 . +/- 15%. If a
particular tool cannot design differential traces, it is permissible to specify 55-65 
single-ended traces as long as the spacing between the two traces is minimized. As an
example, consider a differential trace pair on Layer 1 that is 8 mils (0.2 mm) wide and
2 mils (0.05 mm) thick, with a spacing of 8 mils (0.2 mm). If the fiberglass layer is 8
mils (0.2 mm) thick with a dielectric constant, E
impedance would be approximately 61  and the calculated differential impedance
would be approximately 100 .
When performing a board layout, do not allow the CAD tool auto-router to route the
differential pairs without intervention. In most cases, the differential pairs will have to
be routed manually.
Measuring trace impedance for layout designs targeting 100  often results in lower
actual impedance. Designers should verify actual trace impedance and adjust the
layout accordingly. If the actual impedance is consistently low, a target of 105 – 110 
should compensate for second order effects.
It is necessary to compensate for trace-to-trace edge coupling, which can lower the
differential impedance by up to 10 , when the traces within a pair are closer than 30
mils (edge to edge).
Trace Length and Symmetry for 1000 BASE-T Designs
As indicated earlier, the overall length of differential pairs should be less than four
inches measured from the Ethernet device to the magnetics.
The differential traces (within each pair) should be equal in total length to within 50
mils (1.25 mm) and as symmetrical as possible. Asymmetrical and unequal length
traces in the differential pairs contribute to common mode noise. If a choice has to be
made between matching lengths and fixing symmetry, more emphasis should be placed
on fixing symmetry. Common mode noise can degrade the receive circuit’s performance
and contribute to radiated emissions.
• The reference plane for the differential pairs should be continuous and low
• Do not route differential pairs over splits in the associated reference plane as it
impedance. It is recommended that the reference plane be either ground or
1.9 V dc (the voltage used by the PHY). This provides an adequate return path for
and high frequency noise currents.
may cause discontinuity in impedances.
82574 GbE Controller—Design Considerations
R
, of 4.7, the calculated single-ended