WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 78

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6.1
4.6.2
4.6.3
4.6.3.1
4.6.3.2
78
Interrupts During Initialization
Most drivers disable interrupts during initialization to prevent re-entrancy. Interrupts
are disabled by writing to the IMC register. Note that the interrupts need to be disabled
also after issuing a global reset, so a typical driver initialization flow is:
After the initialization completes, a typical driver enables the desired interrupts by
writing to the IMS register.
Global Reset and General Configuration
Device initialization typically starts with a global reset that puts the device into a known
state and enables the software device driver to continue the initialization sequence.
Several values in the Device Control (CTRL) register need to be set at power up or after
a device reset for normal operation.
If using XOFF flow control, program the FCAH, FCAL, and FCT registers. If not, they
should be written with 0x0.
GCR bit 22 should be set to 1b by software during initialization.
Link Setup Mechanisms and Control/Status Bit Summary
PHY Initialization
Refer to the PHY documentation for the initialization and link setup steps. The device
driver uses the MDIC register to initialize the PHY and setup the link.
MAC/PHY Link Setup
This section summarizes the various means of establishing proper MAC/PHY link
setups, differences in MAC CTRL register settings for each mechanism, and the relevant
MAC status bits. The methods are ordered in terms of preference (the first mechanism
being the most preferred).
1. Disable interrupts
2. Issue a global reset
3. Disable interrupts (again)
4. …
• MAC settings automatically based on duplex and speed resolved by PHY.
• Full duplex should be set per interface negotiation (if done in software), or is set by
• Speed is determined via auto-negotiation by the PHY, or forced by software if the
• ILOS should normally be set to 0b.
the hardware if the interface is auto-negotiating. This is reflected in the Device
Status register in the auto-negotiating case. A default value is loaded from the
NVM.
link is forced. Status information for speed is also readable in STATUS.
(CTRL.FRCDPLX = 0b, CTRL.FRCSPD = 0b, CTRL.ASDE = 0b)
— CTRL.FD - Don't care; duplex setting is established from PHY's internal
— CTRL.SLU - Must be set to 1b by software to enable communications between
— CTRL.RFCE - Must be set by software after reading flow control resolution from
indication to the MAC (FDX) after PHY has auto-negotiated a successful link-up.
MAC and PHY.
PHY registers.
82574 GbE Controller—Initialization