WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 33

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interconnects—82574 GbE Controller
3.1.3.5
3.1.3.6
3.1.3.7
Data Alignment
4 KB Boundary:
Requests must never specify an address/length combination that causes a memory
space access to cross a 4 KB boundary. It is hardware’s responsibility to break requests
into 4 KB-aligned requests (if needed). This does not pose any requirement on
software. However, if software allocates a buffer across a 4 KB boundary, hardware
then issues multiple requests for the buffer. Software should consider aligning buffers
to a 4 KB boundary in cases where it improves performance.
The alignment to the 4 KB boundaries is done in the core. The transaction layer does
not do any alignment according to these boundaries.
64 Bytes:
It is also recommended that requests are multiples of 64 bytes and aligned to make
better use of memory controller resources. This is also done in the core.
Configuration Request Retry Status
The 82574L might have a delay in initialization due to an NVM read. The PCIe defined a
mechanism for devices that require completion of a lengthy self-initialization sequence
before being able to service configuration requests.
If the read of the PCIe section in the NVM was not completed before the 82574
received a configuration request, then the 82574 responds with a configuration request
retry completion status to terminate the request, and effectively stalls the configuration
request until such time that the subsystem has completed local initialization and is
ready to communicate with the host.
Ordering Rules
The 82574L meets the PCIe ordering rules (PCI-X rules) by following the PCI simple
device model:
The 82574L can issue the following master read request from each of the following
clients:
Completed separate read requests are not guaranteed to return in order. Completions
for a single read request are guaranteed to return in address order.
• Deadlock avoidance - Master and target accesses are independent - The response
• Descriptor/data ordering - the 82574 does not proceed with some internal actions
• Rx descriptor read (one per queue)
• Tx descriptor read (one per queue)
• Tx data read (up to four including one for manageability)
to a target access does not depend on the status of a master request to the bus. If
master requests are blocked (such as due to no credits), target completions can
still proceed (if credits are available).
until respective data writes have ended on the PCIe link:
— The 82574L does not update an internal header pointer until the descriptors
— The 82574L does not issue a descriptor write until the data that the descriptor
that the header pointer relates to are written to the PCIe link.
relates to is written to the PCIe link.
33