WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 193

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.7.3.1
Note:
7.7.3.2
System Time Structure and Mode of Operation
The time sync logic contains an up counter to maintain the system time value. This is a
64-bit counter that is built of the SYSTIML and SYSTIMH registers. When in master
state, the SYSTIMH and SYSTIML registers should be set once by the software
according to the general system, when in slave state software should update the
system time on every sync event as described in
time is done by direct write to the SYSTIMH register and fine tune setting of the
SYSTIML register using the adjustment mechanism described in
Read access to the SYSTIMH and SYSTIML registers should be executed in the following
manner:
Upon increment event the system time value should increment its value by the value
stored in TIMINCA.incvalue. Increment event happens every TIMINCA.incperiod cycles
if its one then increment event should occur on every clock cycle. The incvalue defines
the granularity in which the time is represented by the SYSTMH/L registers. For
example, if the cycle time is 16 ns and the incperiod is one then if the incvalue is 16
then the time is represented in nanoseconds if the incvalue is 160 then the time is
represented in 0.1 ns units and so on. The incperiod helps to avoid inaccuracy in cases
where the T value cannot be represented as a simple integer and should be multiplied
to get to an integer representation. The incperiod value should be as small as possible
to achieve best accuracy possible. For more details please refer to
and the following ones.
System time registers should be implemented on a free running clock to make sure the
system time is kept valid on traffic idle times (dynamic clock gating).
Time Stamping Mechanism
The time stamping logic is located on Tx and Rx paths at a location as close as possible
to the PHY. This is to reduce delay uncertainties originating from implementation
differences. The operation of this logic is slightly different on Tx and on Rx.
The Tx part decides to timestamp a packet if the Tx timestamp is enabled and the time
stamp bit in the packet descriptor is set. On the Tx side only the time is captured.
1. Software reads register SYSTIML, at this stage the hardware should latch the value
2. Software reads register SYSTIMH the latched (from last read from SYSTIML) value
of SYSTIMH.
should be returned by HW.
section
7.7.3.3. Setting the system
section
section 10.2.9.13
7.7.3.3.
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