WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 263

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programing Interface—82574 GbE Controller
9.1.2.11
9.1.2.12
9.1.2.13
9.1.2.14
Memory and I/O mapping:
CardBus CIS (Offset 0x28)
Not used. Hardwired to 0b.
Subsystem ID (Offset 0x2E)
This value can be loaded automatically from the NVM at power up with a default value
of 0x0000.
Subsystem Vendor ID (Offset 0x2C)
This value can be loaded automatically from the NVM address 0x0C at power up or
reset. The default value is 0x8086 at power up.
Expansion ROM Base Address (Offset 0x30)
This register is used to define the address and size information for boot-time access to
the optional Flash memory. The BAR size and enablement are set by the NVM.
En
Reserved
Address
Memory
BAR 0
Flash
BAR 1
I/O
BAR 2
MSI-X
BAR 3
Field
Mapping
Window
0
10:1
31:11
Bit(s)
The internal registers and memories are accessed as direct memory
mapped offsets from the base address register. Software can access
byte, word or Dword.
The external Flash can be accessed using direct memory mapped
offsets from the Flash base address register. Software can access byte,
word or Dword.
The Flash BAR is enabled by the DISLFB field in NVM word 0x21.
All internal registers, memories, and Flash can be accessed using I/O
operations. There are two 4-byte registers in the I/O mapping window:
Addr Reg and Data Reg. Software can access byte, word or Dword.
The internal registers and memories are accessed as direct memory
mapped offsets from the base address register. Software accesses are
Dword.
R/W
R
R/W
Read/
Write
0b
0x0
0x0
Initial
Value
Mapping Description
1b = Enables expansion ROM access.
0b = Disables expansion ROM access.
Always read as 0b. Writes are ignored.
Read/Write bits and hardwired to 0b depending on the
memory mapping window size as defined in word 0x21 in
the NVM.
Description
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