WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 415

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.12.9
10.2.12.10 Transmit Data FIFO Tail Saved Register - TDFTS (0x03428; RW)
10.2.12.11 Transmit Data FIFO Packet Count - TDFPC (0x03430; RW)
10.2.12.12 Packet Buffer Memory - PBM (0x10000 - 0x17FFF; RW)
This register’s address has been moved from where it was located in the previous
devices. However, for backwards compatibility, this register can also be accessed at its
alias offset of 0x08018. In addition, with the 82574, the value in this register contains
the offset of the transmit FIFO head relative to the beginning of the entire PBM space.
Alternatively, with the previous devices, the value in this register contains the relative
offset to the beginning of the transmit FIFO space (within the PBM space).
Transmit Data FIFO Head Saved Register - TDFHS (0x03420; RW)
1. The initial value equals PBA.RXA times 128.
This register stores a copy of the Transmit Data FIFO Head register if the internal
register needs to be restored. This register is available for diagnostic purposes only,
and should not be written during normal operation.
1. The initial value equals PBA.RXA times 128.
This register stores a copy of the Receive Data FIFO Tail register if the internal register
needs to be restored. This register is available for diagnostic purposes only, and should
not be written during normal operation.
This register reflects the number of packets to be transmitted that are currently in the
transmit FIFO. This register is available for diagnostic purposes only, and should not be
written during normal operation.
FIFO Head
Reserved
FIFO Tail
Reserved
TX FIFO
Packet Count
Reserved
FIFO Data
Field
Field
Field
Field
12:0
31:13
12:0
31:13
12:0
31:13
31:0
Bit(s)
Bit(s)
Bit(s)
Bit(s)
0x600
0x0
0x600
0x0
0x0
0x0
X
Initial
Initial
Initial
Initial
Value
Value
Value
Value
1
1
A saved value of the Transmit FIFO Head Pointer.
Reads as 0x0. Should be written to 0x0 for future compatibility.
A saved value of the Transmit FIFO Tail Pointer.
Reads as 0x0. Should be written to 0x0 for future compatibility.
The number of packets to be transmitted that are currently in the TX
FIFO.
Reads as 0x0. Should be written to 0x0 for future compatibility.
Packet Buffer Data
Description
Description
Description
Description
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