WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 185

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inline Functions—82574 GbE Controller
7.4.5
Case A: Heavy load, interrupts moderated
Case B: Light load, interrupts immediately on packet receive
Clearing Interrupt Causes
The 82574L has three methods available for to clear ICR bits: auto-clear, clear-on-
write, and clear-on-read.
Auto-Clear
In systems that support MSI-X, the interrupt vector allows the interrupt service routine
to know the interrupt cause without reading the ICR. The software overhead of a I/O
read or write can be avoided by setting appropriate ICR bits to autoclear mode by
setting the corresponding bits in the Interrupt Auto-clear Register (EIAC).
When auto-clear is enabled for an interrupt cause, the ICR bit is set when a cause
event occurs. When the EITR Counter reaches zero, the MSI-X message is sent on
PCIe. Then the ICR bit is cleared and enabled to be set by a new cause event. The
vector in the MSI-X message signals software the cause of the interrupt to be serviced.
It is possible that in the time after the ICR bit is cleared and the interrupt service
routine services the cause, for example checking the transmit and receive queues, that
another cause event occurs that is then serviced by this ISR call, yet the ICR bit
remains set. This results in a spurious interrupt. Software can detect this case if there
are no entries that require service in the transmit and receive queues, and exit knowing
that the interrupt has been automatically cleared. The use of interrupt moderations
through the EITR register limits the extra software overhead that can be caused by
these spurious interrupts.
Pkt
Pkt
Intr
Intr
Pkt
ITR delay
ITR delay
Pkt
Pkt
Intr
Pkt
ITR delay
Pkt
Pkt
Pkt
Intr
Intr
Pkt
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