WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 480

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

480
NC-SI
10/100/
1000Base-T
Interface
Magnetics
Module
10/100/
1000Base-T
Interface
Chassis
Ground
Power
Supply and
Signal
Ground
LED Circuits
Section
Design traces for 50  single ended
impedance (+ 20% - 10%).
There should be less than eight inches of
trace between the 82574 and the
Manageability Controller (MC).
There should be less than four inches of
trace between the 82574 and any other
devices sharing the NC-SI bus.
Capacitors connected to center taps
should be placed very close (less than 0.1
inch recommended) to the integrated
magnetics module.
The system side center tap on the
transformer should be connected to the
1.9 V dc power supply through a plane.
Provide a separate chassis ground “island”
to ground the shroud of the RJ-45
connector and if needed to terminate the
line side of the magnetics module. This
design improves EMI behavior.
Ensure there is a gap to provide high
voltage isolation to line side of the MDI
traces and the Bob Smith termination.
Place 4-6 pairs of pads for stitching
capacitors to bridge the gap from chassis
ground to signal ground.
When using the internal regulator control
circuits of the 82574 with external PNP
transistors, keep the trace length from the
CTRL10 and CTRL19 output balls to the
transistors very short (less one inch) and
use
Use planes if possible.
The 1.05 V dc and 1.9 V dc regulating
circuits require 1/2 inch x 1/2 inch thermal
relief pads for each PNP.
The 3.3 V dc rail should have at least 25
F of capacitance.
The 1.05 V dc and 1.9 V dc rails should
have 20-40 F of capacitance.
Place these to minimize the inductance
from each power pin to the nearest
decoupling capacitor.
If using decoupling capacitors on LED
lines, place them carefully.
Keep LED traces away from sources of
noise, for example, high speed digital
traces running in parallel.
50 mil (minimum) wide traces.
Check Item
82574 GbE Controller—Board Layout and Schematic Checklists
There should be less than 30 pF total trace capacitance.
This improves Bit Error Rate (BER).
The center tap voltage is critical to performance of MDI
interface. Any voltage drop can cause violations to the
specification. Some designs that have a resistive path to the
MDI transformer may require addition regulators to boost the
voltage to above 1.9 V dc at the transformer center tap.
The split in ground plane should be at least 50 mils. For
discrete magnetics modules, the split should run under center
of magnetics module. Differential pairs never cross the split.
The Bob Smith termination and the MDI traces should be >=
80 mils away from all components and traces on the same
layer. Ensure there is at least 10 mils of single ply woven epoxy
(FR-4) between the chassis ground and any other nodes. Since
there can be small air pockets between woven fibers, it better
to use thicker, two ply, or three ply epoxy (FR-4) to provide
high voltage isolation.
Determine exact number and values empirically based on EMI
performance.
A low inductive loop should be kept from the regulator control
pin, through the PNP transistor, and back to the chip from the
transistor's collector output. The power pins should connect to
the collector of the transistor through a power plane to reduce
the inductive path. This reduces oscillation and ripple in the
power supply.
Narrow finger-like planes and very wide traces are allowed. If
traces are used, 100 mils is the minimum.
The pads should be placed on the top layer, under the PNP.
Place decoupling and bulk capacitors close to 82574, with
some along every side, using short, wide traces and large vias.
If power is distributed on traces, bulk capacitors should be
used at both ends. If power is distributed on cards, bulk
capacitors should be used at the connector.
Capacitors on LED lines should be placed near the LEDs.
LED traces can carry noise into integrated magnetics modules,
RJ-45 connectors, or out to the edge of the board, increasing
EMI.
Remarks