WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 274

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1.6.1.7
274
Link CAP, Offset 0xEC, (RO)
This register identifies PCIe link-specific capabilities. This is a read-only register.
3:0
11:10
14:12
17:15
18
19
20
23:21
31:24
9:4
Bits
RO
RO
RO
RO
RO
RO
RO
RO
RO
HwInit
R/W
0001b
0x01
11b
001b
(64-
128 ns)
110b
(32-64 s)
0b
0b
000b
0x0
0b
Default
Max Link Speed
The 82574L indicates a maximum link speed of 2.5 Gb/s.
Max Link Width
Indicates the maximum link width. The 82574L supports x1 lane link.
Defined encoding:
000001b x1.
All other values - Reserved.
Active State Link PM Support
Indicates the level of active state power management supported in the
82574. Defined encodings are:
00b = No ASPM support.
01b = L0s supported.
10b = L1 supported.
11b = L0s and L1 supported.
This field is loaded from the NVM PCIe Init Configuration 3 word 0x1A.
L0s Exit Latency
Indicates the exit latency from L0s to L0 state. This field is loaded from the
NVM PCIe Init Configuration 1 word 0x18 (two values for common PCIe clock
or separate PCIe clock.
000b = Less than 64 ns.
001b = 64 ns – 128 ns.
010b = 128 ns – 256 ns.
011b = 256 ns - 512 ns.
100b = 512 ns - 1 s.
101b = 1 s – 2 s.
110b = 2 s – 4 s.
111b = Reserved.
If the 82574 uses a common clock - PCIe Init Config 1 bits [2:0], if the 82574
uses a separate clock - PCIe Init Config 1 bits [5:3].
L1 Exit Latency
Indicates the exit latency from L1 to L0 state. This field is loaded from the
NVM PCIe Init Configuration 1 word 0x18.
000b = Less than 1 s.
001b = 1 s - 2 s.
010b = 2 s - 4 s.
011b = 4 s - 8 s.
100b = 8 s - 16 s.
101b = 16 s - 32 s.
110b = 32 s - 64 s.
111b = L1 transition not supported.
Port Number
The PCIe port number for the given PCIe link. Field is set in the link training
phase.
Reserved.
Surprise Down Error Reporting Capable.
Data Link Layer Link Active Reporting Capable.
Reserved.
82574 GbE Controller—Programing Interface
Description