WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 309

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.2.17
Note:
Note:
Note:
10.2.2.18
Note:
Packet Buffer Allocation - PBA (0x01000; RW)
This register sets the on-chip receive and transmit storage allocation ratio. The receive
allocation value is read/write for the lower 6 bits. The transmit allocation is read only
and is calculated based on RXA. The partitioning size is 1 KB.
Programming this register does not automatically re-load or initialize internal packet-
buffer RAM pointers. Software must reset both transmit and receive operation (using
the global device reset CTRL.RST bit) after changing this register in order for it to take
effect. The PBA register itself is not reset by asserting the global reset, but is only reset
upon initial hardware power on.
For best performance the transmit buffer allocation should be set to accept two full
sized packets.
Transmit packet buffer size should be configured to be more than 4 KB.
MNG EEPROM Control Register - EEMNGCTL (0x1010; RO)
This register is read/write by firmware and read only by software.
RXA
TXA
ADDR
START
WRITE
EEBUSY
Reserved
EE_TRANS_E
Reserved
DONE
Field
Field
15:0
31:16
14:0
15
16
17
18
19
30:20
31
Bit(s)
Bit(s)
0x0014
0x0014
0x0
0b
0b
0b
0b
0b
0x0
1b
Initial
Initial
Value
Value
Receive packet buffer allocation in KB. Upper 10 bits are read only as
0x0. Default is 20 KB.
Transmit packet buffer allocation in KB. These bits are read only.
Default is 20 KB.
Address
This field is written by manageability along with Start Read or Start
write to indicate the EEPROM word address to read or write.
Start
Writing a 1b to this bit causes the EEPROM to start the read or write
operation according to the write bit.
Write
This bit tells the EEPROM if the current operation is read or write.
0b = Read.
1b = Write.
EPROM Busy
This bit indicates that the EEPROM is busy doing an auto read.
Reserved
Transaction
This bit indicates that the register is in the middle of a transaction.
Reserved
Transaction Done
This bit is cleared after the Start Write or the Start Read bit is set by
manageability and is set back again when the EEPROM write or read
transaction completes.
Description
Description
309