WG82574IT S LBAC Intel, WG82574IT S LBAC Datasheet - Page 325

• Manufacturer Part Number: WG82574IT S LBAC
• Description: CONTROLLER, ENET, INTEL 82574IT, 64PQFN
• Manufacturer: Intel

Specifications of WG82574IT S LBAC

• Ethernet Type: IEEE 802.3, IEEE 802.3u, IEEE 802.3ab
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• No. Of Pins: 64
• Package / Case: QFN
• Interface Type: I2C, JTAG, PCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Driver Programing Interface—82574 GbE Controller
10.2.4.6
Interrupt Mask Clear Register - IMC (0x000D8; W)
Software uses this register to disable an interrupt. Interrupts are presented to the bus
interface only when the mask bit is 1b and the cause bit is 1b. The status of the mask
bit is reflected in the Interrupt Mask Set/Read register (see
status of the cause bit is reflected in the Interrupt Cause Read register (see
Section
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished
by writing a 1b to the corresponding bit in this register. Bits written with 0b are
unchanged (for example, their mask status does not change).
In summary, the sole purpose of this register is to enable software a way to disable
certain, or all, interrupts. Software disables a given interrupt by writing a 1b to the
corresponding bit in this register.
TXDW
TXQE
LSC
Reserved
RXDMT0
Reserved
RXO
RXT0
reserved
MDAC
Reserved
Reserved
Reserved
Reserved
TXD_LOW
SRPD
ACK
MNG
Reserved
RxQ0
RxQ1
TxQ0
TxQ1
Other
Reserved
Field
10.2.4.4).
0
1
2
3
4
5
6
7
8
9
10
11
12
14:13
15
16
17
18
19
20
21
22
23
24
31:25
Bit(s)
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
00b
0b
0b
0
X
X
0
0
0
0
0
0
Initial
Value
Clears the mask for transmit descriptor written back.
Clears the mask for transmit queue empty.
Clears the mask for link status change.
Reserved
Clears the mask for receive descriptor minimum threshold hit.
Reserved
Reads as 0b.
Clears the mask for receiver overrun. Set on receive data FIFO
overrun.
Clears the mask for receiver timer interrupt.
Reserved
Clears the mask for MDIO access complete interrupt.
Reserved
Reserved
Reads as 0b.
Reserved
Reserved
Clears the mask for transmit descriptor low threshold hit.
Clears the mask for small receive packet detect interrupt.
Clears the mask for receive ACK frame detect interrupt.
Clears the mask for a manageability event.
Reserved
Clears the mask for receive queue 0 interrupt.
Clears the mask for receive queue 1 interrupt.
Clears the mask for transmit queue 0 interrupt.
Clears the mask for transmit queue 1 interrupt.
Clears the mask for other interrupt.
Reserved
Should be written with 0x0 to ensure future compatibility.
Description
Section
10.2.4.5), and the
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