IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 93
![KIT DEVELOPMENT I.MX257, ARM926](/photos/37/58/375862/imx25kbsbd_sml.jpg)
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 93 of 154
- Download datasheet (2Mb)
1
2
3
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
4
1
2
Freescale Semiconductor
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2CLK signal.
max_rise_time(ID No IC9) + data_setup_time(ID No IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus
specification) before the I2CLK line is released.
C
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal
b
IC10
IC11
IC12
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
= total capacitance of one bus line in pF.
ID
I2CLK cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2CLK Clock
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (C
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Table 70. I2C Module Timing Parameters: 1.8 V +/– 0.10 V
Parameter
b
)
Min.
Standard Mode
250
4.0
4.0
4.0
4.7
4.7
4.7
10
0
-
-
-
1
3.45
Max.
1000
300
400
-
-
-
-
-
-
-
-
2
Unit
pF
μ s
μ s
μ s
μ s
μ s
μ s
μ s
ns
μ s
ns
ns
93
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