IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 59
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 59 of 154
- Download datasheet (2Mb)
1
2
Freescale Semiconductor
SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 48
SD10
SD9
ID
SDCLK
SDCLK
and
ADDR
DQM
RAS
CAS
Data out hold time
Active to read/write command period
Table
WE
DQ
CS
Table 44. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
49.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
SD4
SD6
BA
Figure 26. SDR SDRAM Write Cycle Timing Diagram
2
SD5
Parameter
SD7
SD11
ROW / BA
SD12
SD1
SD3
SD4
SD13
Symbol
tOH
tRC
SD4
SD4
COL/BA
SD2
DATA
SD5
SD5
SD5
SD14
Min.
1.2
10
Max.
—
—
clock
Unit
ns
59
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