IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 66
![KIT DEVELOPMENT I.MX257, ARM926](/photos/37/58/375862/imx25kbsbd_sml.jpg)
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 66 of 154
- Download datasheet (2Mb)
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66
These values are for a DQ/DM slew rate of 1 V/ns and a DQS slew rate of 1 V/ns. For additional values use
DtDH1 Derating Values for DDR2-400, DDR2-533.”
DDR17
DDR18
DDR19
DDR20
DDR21
DDR22
DDR23
ID
DQ & DQM setup time to DQS (single-ended strobe)
DQ & DQM hold time to DQS (single-ended strobe)
Write cycle DQS falling edge to SDCLK output setup time
Write cycle DQS falling edge to SDCLK output hold time
DQS latching rising transitions to associated clock edges
DQS high-level width
DQS low-level width
DQM (output)
DQS (output)
DQ (output)
SDCLK_B
SDCLK
ΔtD
2.0 V/ns
S1
Table 53. ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-533
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
ΔtD
H1
Figure 32. DDR2 SDRAM Write Cycle Timing Diagram
Table 52. DDR2 SDRAM Write Cycle Parameter Table
ΔtD
1.5 V/ns
S1
DDR17
DDR21
DDR17
ΔtD
H1
Parameter
ΔtD
S1
1.0 V/ns
Data
DM
ΔtD
H1
DDR18
DDR18
Data
DM
ΔtD
0.9 V/ns
S1
DQS Single-Ended Slew Rate
ΔtD
H1
DDR17
DDR17
Data
DM
1
1
ΔtD
DDR22
0.8 V/ns
S1
ΔtD
Data
DM
H1
DDR23
ΔtD
S1
0.7 V/ns
DDR18
DDR18
t
t
Symbol
Data
DS1(base)
DH1(base)
DM
t
t
t
t
DQSS
DQSH
t
DQSL
DSS
DSH
ΔtD
H1
ΔtD
S1
0.6 V/ns
Data
DM
DDR19
ΔtD
0.025
0.025
H1
-0.25
Min.
0.35
0.35
0.2
0.2
1,2,3
DDR2-400
Freescale Semiconductor
Data
DM
ΔtD
S1
0.5 Vns
Table
Max.
ΔtD
0.25
H1
Data
DM
—
—
—
—
—
—
DDR20
53, “DtDS1,
ΔtD
S1
0.4 V/ns
Unit
tCK
tCK
tCK
tCK
tCK
ns
ns
ΔtD
H1
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