IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 64
![KIT DEVELOPMENT I.MX257, ARM926](/photos/37/58/375862/imx25kbsbd_sml.jpg)
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 64 of 154
- Download datasheet (2Mb)
3.7.6.1.3
The following diagrams and tables specify timing related to the SDRAMC module, which interfaces with
DDR2 SDRAM.
Table 50
differential slew rate of 2 V/ns. For additional values, use
DDR2-400, DDR2-533.”
64
DDR1
DDR2
DDR3
ID
SDCLK
SDCLK
ADDR
provides values for a command/address slew rate of 1 V/ns and an SDCLK, SDCLK_B
RAS
CAS
WE
CKE
CS
DDR6
DDR4
DDR4
DDR2 SDRAM–Specific Parameters
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
ROW/BA
SDRAM clock high-level width
SDRAM clock low-level width
SDRAM clock cycle time
Figure 31. DDR2 SDRAM Basic Timing Parameters
DDR5
Table 50. DDR2 SDRAM Timing Parameter Table
DDR5
Parameter
DDR7
DDR4
DDR4
COL/BA
DDR4
DDR5
DDR5
Table
DDR1
DDR3
51, “tlS, tlH Derating Values for
Symbol
t
t
t
CH
CL
CK
DDR2
Min.
0.45
0.45
7.5
DDR2-400
Freescale Semiconductor
Max.
0.55
0.55
8
Unit
t
t
ns
CK
CK
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