IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 109
![KIT DEVELOPMENT I.MX257, ARM926](/photos/37/58/375862/imx25kbsbd_sml.jpg)
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 109 of 154
- Download datasheet (2Mb)
Note:
Freescale Semiconductor
• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
• All timings are on pads when SSI is being used for data transfer.
• ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI.
• For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables figures.
mode of operation).
SS22
SS23
SS24
SS25
SS26
SS27
SS29
SS31
SS33
SS37
SS38
SS39
SS44
SS45
SS46
ID
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
FS (bl) low/ high setup before (Tx) CK falling
FS (bl) low/ high setup before (Tx) CK falling
FS (wl) low/ high setup before (Tx) CK falling
FS (wl) low/ high setup before (Tx) CK falling
(Tx) CK high to STXD valid from high impedance
(Tx) CK high to STXD high/low
(Tx) CK high to STXD high impedance
SRXD setup before (Tx) CK falling
SRXD hold after (Tx) CK falling
SRXD rise/fall time
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Table 83. SSI Transmitter Timing with External Clock
Parameter
Synchronous External Clock Operation
External Clock Operation
–10.0
–10.0
Min.
81.4
36.0
36.0
10.0
10.0
10.0
2.0
—
—
—
—
—
—
Max.
15.0
15.0
15.0
15.0
15.0
6.0
6.0
6.0
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
109
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