IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 17
IAR-KSK-IMX25
Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr
Datasheets
1.MCIMX25WPDKJ.pdf
(2 pages)
2.IAR-KSK-IMX25.pdf
(154 pages)
3.IAR-KSK-IMX25.pdf
(2 pages)
4.IAR-KSK-IMX25.pdf
(57 pages)
Specifications of IAR-KSK-IMX25
Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MCIMX25WPDKJ PDF datasheet
- IAR-KSK-IMX25 PDF datasheet #2
- IAR-KSK-IMX25 PDF datasheet #3
- IAR-KSK-IMX25 PDF datasheet #4
- Current page: 17 of 154
- Download datasheet (2Mb)
Figure 2
powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up.
3.2.2
There are no special requirements for the power-down sequence. All power supplies can be shut down at
the same time.
3.2.3
In order to guarantee DryIce power-loss protection, which includes that SRTC time is kept during
power-down; in addition to having the proper capacitor placed on the NVCC_DRYICE output pin, users
must follow the specific power-up/down sequence.
For users who want to utilize the DryIce power-loss protection feature, the following power-up sequence
is recommended:
Freescale Semiconductor
QVDD and NVDD
Analog Supplies
1. Assert Power on reset (POR).
2. Turn on NVCC_CRM.
3. At any time from step 2 and to step 4, turn on other digital I/O power suppliers NVCCx.
4. Turn on digital logic domain QVDD no less than 1 ms and no greater than 32 ms after
NVCC_CRM reaches 90 % of 3.3 V. Step 2 and step 4 order are critical for proper power-loss
protection.
shows the power-up sequence diagram. After POR_B is asserted, Core VDD and NVDDx can be
POR_B
Power-Down Sequence
SRTC DryIce Power-Up/Down Sequence
This is to guarantee that POR is stable already at NVCC_CRM/QVDD
power domain interface before QVDD is on, and POR instantly propagates
to QVDD domain after QVDD is on.
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Figure 2. Power-Up Sequence Diagram
NOTE
17
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