IAR-KSK-IMX25 Freescale Semiconductor, IAR-KSK-IMX25 Datasheet - Page 102

KIT DEVELOPMENT I.MX257, ARM926

IAR-KSK-IMX25

Manufacturer Part Number
IAR-KSK-IMX25
Description
KIT DEVELOPMENT I.MX257, ARM926
Manufacturer
Freescale Semiconductor
Series
i.MX25r
Type
MCUr

Specifications of IAR-KSK-IMX25

Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
I.MX257
Processor Series
i.MX25
Data Bus Width
16 bit
Interface Type
UART, JTAG, USB, Ethernet, SD/MMC
Core
ARM926EJ-S
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
I.MX2
Silicon Family Name
I.MX25
Mcu Supported Families
I.MX25
For Use With/related Products
i.MX25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1
2
102
In cases where SDMA TAP is put in the chain, the maximum TCK frequency is limited by the maximum ratio of 1:8 of SDMA
core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock.
V
SJ10
SJ11
SJ12
SJ13
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
SJ9
M –
ID
mid point voltage
(Input)
TCK cycle time
TCK clock pulse width measured at
TCK rise and fall times
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
TRST
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
(Input)
TCK
SJ12
Parameter
SJ13
Table 78. SJC Timing Parameters
Figure 75. TRST Timing Diagram
V
M
2
100
Min.
100
40
10
50
10
50
40
All Frequencies
1
Max.
50
50
44
44
3
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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