XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 97

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Example 5-3 shows a DMA configuration for transferring data to the Host Transmit register of
the HI08.
DMA requires more initialization code and consideration of DMA modes. However, it is the
most efficient use of core resources. Once these registers are programmed, you must enable the
DMA by triggering a DMA request off one of the peripheral control flags or enabling it in normal
program flow or an interrupt service routine.
5.4.4 Advantages and Disadvantages
Polling is the easiest method to implement, but it requires a large amount of DSP56309 core
processing power. The core cannot be involved in other processing activities while it is polling
receive and transmit ready bits. Interrupts require more code, but the core can process other
routines while waiting for data I/O. An interrupt is generated when data is ready to be transferred
to or from the peripheral device. DMA requires even less core intervention, and the setup code is
minimal, but the DMA channels must be available.
Note:
Freescale Semiconductor
bclr#M_D1L0,x:M_IPRC
bclr#M_D1L1,x:M_IPRC
movep#TBUFF_START,x:M_DSR1 ; DMA1 source is transmit buffer
movep#M_HTX,x:M_DDR1
movep#TBUFF_SIZE-1,x:M_DCO1; DMA1 count is the full buffer
movep#INIT_DCR1,x:M_DCR1
Do not use interrupt requests and DMA requests simultaneously.
EFCOP
Block
Timer
ESSI
HI08
SCI
Table 5-1. DMA-Accessible Registers
; disable DMA1 interrupts
; DMA1 destination is HTX
; init. DMA1 control register
Example 5-3. DMA Transfers
DSP56309 User’s Manual, Rev. 1
Register
FDOR
FDIR
SRX
HRX
STX
HTX
TX0
TX1
TX2
RX
Read
Yes
Yes
Yes
Yes
No
No
No
No
No
No
DMA
Data Transfer Methods
Write
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
5-5