XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 95

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.1 Polling
Polling is the easiest method for data transfers. When polling is chosen, the DSP56309 core
continuously checks a specified register flag waiting for an event to happen. One example would
be setting an overflow flag in one of the Timers. Once the event occurs, the DSP56309 is free to
continue with its next task. However, while it is waiting for the event to occur, the DSP56309
core is not executing any other code. Polling is the easiest transfer method since it does not
require register initialization, but it is also the least efficient use of the DSP core.
Each peripheral has its own set of flags which can be polled to determine when data is ready to be
transferred. For example, the ESSI control registers provide bits that tell the core when data is
ready to be transferred to or from the peripheral. The core polls these bits to determine when to
interact with the peripheral. Similar flags exist for each peripheral.
Example 5-1 shows software polling programmed in an application using the HI08.
In this example, the core waits until the Host Status Register (HSR) Host Transmit Data Empty
(HTDE) flag is set. When the flag is set, the core moves data from Y memory to the X1 register.
5.4.2 Interrupts
Interrupts are more efficient than polling, but interrupts also require additional register
initialization. Polling requires the core to remain busy checking a flag in a specified control
register and therefore does not allow the core to execute other code at the same time. For
interrupts, you can initialize the interrupt so it is triggered off one of the same flags that can also
be polled. Then the core does not have to continuously check a flag. Once the interrupt is
initialized and the flag is set, the core is notified to execute a data transfer. Until the flag is set, the
core can remain busy executing other sections of code.
When an interrupt occurs, the core execution flow jumps to the interrupt start address defined in
Table B-3 in Appendix B, Programming Reference. It executes code starting at the interrupt
address. If it is a short interrupt (that is, the service routine is two opcodes long), the code
automatically returns to the original program flow after executing two opcodes with no impact to
the pipeline. Otherwise, if a longer service routine is required the programmer can place a
jump-to-subroutine (JSR) instruction at the interrupt service address. In this case, the program
executes that service routine and continues until a return-from-interrupt (RTI) instruction
executes. The execution flow then resumes from the position the program counter was in before
the interrupt was triggered.
Freescale Semiconductor
jclr#1,x:M_HSR,*
movey:(TBUFF_PTR)+,x1
; loop if HSR[1]:HTDE=0
; move data to x1
Example 5-1. Software Polling
DSP56309 User’s Manual, Rev. 1
Data Transfer Methods
5-3