XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 229

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HI08LL
HI08NW
HI08LOOP
;========================================================================
EPRSCILD
;
;========================================================================
; This is the routine that loads from the SCI.
; MD:MC:MB:MA=1010 - external SCI clock
SCILD
_LOOP6
_LOOP8
_LOOP7
;========================================================================
; This is the routine that loads from external EPROM.
Freescale Semiconductor
movep
move
do
jset
jclr
enddo
bra
movep
nop
bra
jclr #1,omr,EPROMLD
jset #0,omr,SCILD
movep #$0302,X:M_SCR
movep #$C000,X:M_SCCR
movep #7,X:M_PCRE
do #6,_LOOP6
jclr #2,X:M_SSR,*
movep X:M_SRXL,A2
jclr #1,X:M_SSR,*
movep A2,X:M_STXL
asr #8,a,a
move a1,r0
move a1,r1
do a0,_LOOP7
do #3,_LOOP8
jclr #2,X:M_SSR,*
movep X:M_SRXL,A2
jclr #1,X:M_SSR,*
movep a2,X:M_STXL
asr #8,a,a
movem a1,p:(r0)+
nop
bra <FINISH
x:M_HRX,r0
r0,r1
a0,HI08LOOP
#HRDF,x:M_HSR,HI08NW
#HF0,x:M_HSR,HI08LL
<HI08LOOP
x:M_HRX,p:(r0)+
<FINISH
; If MD:MC:MB:MA=1001, go load from EPROM
; If MD:MC:MB:MA=1011, reserved, default to SCI
; Configure SCI Control Reg
; Configure SCI Clock Control Reg
; Configure SCLK, TXD and RXD
; get 3 bytes for number of
; program words and 3 bytes
; for the starting address
; Wait for RDRF to go high
; Put 8 bits in A2
; Wait for TDRE to go high
; echo the received byte
; starting address for load
; save starting address
; Receive program words
; Wait for RDRF to go high
; Put 8 bits in A2
; Wait for TDRE to go high
; echo the received byte
; Store 24-bit result in P mem.
; pipeline delay
; Boot from SCI done
DSP56309 User’s Manual, Rev. 1
; to be written
; set a loop with the downloaded length
; If new word was loaded then jump to
; read that word
; If HF0=0 then continue with the
; downloading
; Must terminate the do loop
; Move the new word into its destination
; location in the program RAM
; pipeline delay
Bootstrap Code
A-7