XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 204

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Triple Timer Module
9.3.2.1 Measurement Input Width (Mode 4)
In Mode 4, the timer counts the number of clocks that occur between opposite edges of an input
signal. After the first appropriate transition (as determined by the TCSR[INV] bit) occurs on the
TIO
on the first high-to-low (1 to 0) signal transition on the
timer starts on the first low-to-high (that is, 0 to 1) transition on the
transition opposite in polarity to the INV bit setting occurs on the
TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE] bit is set. The value of
the counter (which measures the width of the TIO pulse) is loaded into the TCR, which can be
read to determine the external signal pulse width. If the TCSR[TRM] bit is set, the counter is
loaded with the TLR value on the first timer clock received following the next valid transition on
the
increment on each timer clock. This process repeats until the timer is disabled.
9-12
TC3
0
TIO
input signal, the counter is loaded with the TLR value. If TCSR[INV] is set, the timer starts
Mode 4 (internal clock): TRM = 1
TCF (Compare Interrupt if TCIE = 1)
N = write preload
M = write compare
input signal, and the count resumes. If TCSR[TRM] is cleared, the counter continues to
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
TCR
TIO pin
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
TC2
Bit Settings
1
TC1
0
Figure 9-11. Pulse Width Measurement Mode, TRM = 1
TC0
0
N
0
Mode
DSP56309 User’s Manual, Rev. 1
first event
4
width being measured
N
Input width
Name
N + 1
Mode Characteristics
TIO
signal. If the INV bit is cleared, the
Measurement
Function
TIO
M
TIO
signal, the counter stops.
M
signal. When the first
Freescale Semiconductor
Interrupt Service
reads TCR; width
= M - N clock
periods
Next 0-to-1 edge
on TIO loads
counter and
process repeats
Input
TIO
N + 1
Internal
Clock