XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 80

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
4-22
Number
20–16
15–13
12–10
Bit
23
22
21
Bit Name
BDFW
BA3W
BA2W
BRH
BBS
Reset Value
Table 4-8. Bus Control Register (BCR) Bit Definitions
(31 wait
states)
(7 wait
states)
(7 wait
states)
11111
111
0
0
0
1
Bus Request Hold
Asserts the BR signal, even if no external access is needed. When BRH is set, the
BR signal is always asserted. If BRH is cleared, the BR is asserted only if an
external access is attempted or pending.
Reserved. Write to zero for future compatibility.
Bus State
This read-only bit is set when the DSP is the bus master and is cleared otherwise.
Bus Default Area Wait State Control
Defines the number of wait states (one through 31) inserted into each external
access to an area that is not defined by any of the AAR registers. The access type
for this area is SRAM only. These bits should not be programmed as zero since
SRAM memory access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
Bus Area 3 Wait State Control
Defines the number of wait states (one through seven) inserted in each external
SRAM access to Area 3 (DRAM accesses are not affected by these bits). Area 3 is
the area defined by AAR3.
Note:
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
Bus Area 2 Wait State Control
Defines the number of wait states (one through seven) inserted into each external
SRAM access to Area 2 (DRAM accesses are not affected by these bits). Area 2 is
the area defined by AAR2.
Note:
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
DSP56309 User’s Manual, Rev. 1
Do not program the value of these bits as zero since SRAM memory
access requires at least one wait state.
Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
Description
Freescale Semiconductor