XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 220

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Triple Timer Module
9.4.5 Timer Load Register (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR value
after the TCSR[TE] bit is set and a first event occurs.
9.4.6 Timer Compare Register (TCPR)
The TCPR is a 24-bit read/write register that contains the value to be compared to the counter
value. These two values are compared every timer clock after TCSR[TE] is set. When the values
match, the timer compare flag bit is set and an interrupt is generated if interrupts are enabled (that
is, the timer compare interrupt enable bit in the TCSR is set). The TCPR is ignored in
measurement modes.
9-28
Mode
10
6
7
9
In timer modes, if the TCSR[TRM] bit is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs.
In measurement modes, if TCSR[TRM] and TCSR[TE] are set, the counter is reloaded
with the value in the TLR on each appropriate edge of the input signal.
In PWM modes, if TCSR[TRM] is set, the counter is reloaded each time after it overflows
and the new event occurs.
In watchdog modes, if TCSR[TRM] is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs. In
this mode, the counter is also reloaded whenever the TLR is written with a new value
while TCSR[TE] is set.
In all modes, if TCSR[TRM] is cleared (TRM = 0), the counter operates as a free-running
counter.
Event is captured on the rising
edge of the signal from the TIO
signal.
INV = 0
—
—
—
Table 9-4. Inverter (INV) Bit Operation (Continued)
TIO Programmed as Input
Event is captured on the
falling edge of the signal
from the TIO signal.
DSP56309 User’s Manual, Rev. 1
INV = 1
—
—
—
Pulse generated by
the timer has positive
polarity.
Pulse generated by
the timer has positive
polarity.
Pulse generated by
the timer has positive
polarity.
INV = 0
TIO Programmed as Output
—
Freescale Semiconductor
Pulse generated by the
timer has negative
polarity.
Pulse generated by the
timer has negative
polarity.
Pulse generated by the
timer has negative
polarity.
INV = 1
—