XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 261

IC DSP 24BIT 100MHZ 196-MAPBGA

XC56309VL100A

Manufacturer Part Number
XC56309VL100A
Description
IC DSP 24BIT 100MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheets

Specifications of XC56309VL100A

Interface
Host Interface, SSI, SCI
Clock Rate
100MHz
Non-volatile Memory
ROM (576 B)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
196-MAPBGA
Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
102KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC56309VL100A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
XC56309VL100AR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
Transmitter Clock Mode/Source
0 = Internal clock for Transmitter
1 = External clock from SCLK
TCM
0
0
1
1
Application:
SCI
RCM
0
1
0
1
TX Clock
External
External
Internal
Internal
Figure B-18. SCI Clock Control Registers (SCCR)
RX Clock
External
External
Internal
Internal
SCI Clock Control Register (SCCR)
Reset = $000000
23
*
0
TCM RCM
SCLK Pin
15 14 13 12 11 10
Output
Input
Input
Input
Receiver Clock Mode/Source
0 = Internal clock for Receiver
1 = External clock from SCLK
DSP56309 User’s Manual, Rev. 1
SCI Clock Prescaler
SCP
0 = ÷1 1 = ÷ 8
Synchronous/Asynchronous
Synchronous/Asynchronous
COD CD11 CD10 CD9
Asynchronous only
Asynchronous only
Clock Out Divider
0 = Divide clock by 16 before feed to SCLK
1 = Feed clock to directly to SCLK
Mode
9
CD8
8
CD7
Address X:$FFFF9B Read/Write
7
CD11–CD0
$FFE
$FFF
$000
$001
$002
CD6
6
Clock Divider Bits (CD11–CD0)
*
= Reserved, Program as 0
Date:
Programmer:
CD5
5
CD4
4
CD3
3
I
I
I
cyc
cyc
cyc
I
I
I
cyc
cyc
cyc
/4095
/4096
Programming Sheets
Rate
/1
/2
/3
CD2
2
Sheet 2 of 2
CD1
1
CD0
0
B-27

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