XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 62

• Manufacturer Part Number: XC56309VL100A
• Description: IC DSP 24BIT 100MHZ 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of XC56309VL100A

• Interface: Host Interface, SSI, SCI
• Clock Rate: 100MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 102KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Core Configuration
4-4
Mode
A
B
C
8
9
MODD
1
1
1
1
1
MODC
0
0
0
0
1
Table 4-1. DSP56309 Operating Modes (Continued)
MODB
0
0
1
1
0
MODA
0
1
0
1
0
DSP56309 User’s Manual, Rev. 1
$008000
$FF0000
$FF0000
$FF0000
$FF0000
Vector
Reset
Expanded mode
Bypasses the bootstrap ROM, and the DSP56309 starts fetching
instructions beginning at address $008000. Memory accesses
are performed using SRAM memory access type with 31 wait
states and no address attributes selected.
Bootstrap from byte-wide memory
The bootstrap program it loads a program RAM segment from
consecutive byte-wide P memory locations, starting at
P:$D00000 (bits 7-0). The memory is selected by the Address
Attribute AA1 and is accessed with 31 wait states. The EPROM
bootstrap code expects to read 3 bytes specifying the number of
program words, 3 bytes specifying the address to start loading
the program words and then 3 bytes for each program word to
be loaded. The number of words, the starting address and the
program words are read least significant byte first followed by
the mid and then by the most significant byte. The program
words are condensed into 24-bit words and stored in contiguous
PRAM memory locations starting at the specified starting
address. After reading the program words, program execution
starts from the same address where loading started.
Bootstrap through SCI
The DSP is configured to load the program RAM from the SCI
interface. The number of program words to be loaded and the
starting address must be specified. The SCI bootstrap code
expects to receive 3 bytes specifying the number of program
words, 3 bytes specifying the address to start loading the
program words and then 3 bytes for each program word to be
loaded. The number of words, the starting address and the
program words are received least significant byte first followed
by the mid and then by the most significant byte. After receiving
the program words, program execution starts in the same
address where loading started. The SCI is programmed to work
in asynchronous mode with 8 data bits, 1 stop bit and no parity.
The clock source is external and the clock frequency must be
16x the baud rate. After each byte is received, it is echoed back
through the SCI transmitter.
Reserved
HI08 bootstrap in ISA/DSP563xx mode
The HI08 is configured to load the program RAM from the Host
Interface programmed to operate in the ISA mode. The HOST
ISA bootstrap code expects to read a 24-bit word specifying the
number of program words, a 24-bit word specifying the address
to start loading the program words and then a 24-bit word for
each program word to be loaded. The program words are stored
in contiguous P RAM memory locations starting at the specified
starting address. After reading the program words, program
execution starts from the same address where loading started.
The Host Interface bootstrap load program may be stopped by
setting the Host Flag 0 (HF0). This starts execution of the loaded
program from the specified starting address.
Description
Freescale Semiconductor