HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 95

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5.6
When the following operations are performed in the order shown when a pin to which IRQ input is
assigned is designated as a general input pin by the pin function controller (PFC) and inputs a low-
level signal, the IRQ falling edge is detected, and an interrupt request is detected, immediately
after the setting in (b) is performed:
• An interrupt control register (ICR) setting is made so that an interrupt is detected at the falling
• The function of pins to which IRQ input is assigned is switched from general input to IRQ
Therefore, when switching the pin function from general input pin to IRQ input, the pin function
controller (PFC) setting should be changed to IRQ input while the pin to which IRQ input is
assigned is high.
74 RENESAS
Instruction (instruction replaced by
edge of IRQ.
input by a pin function controller (PFC) setting.
F (Instruction fetch)
D (Instruction decoding)
E (Instruction execution)
M (Memory access)
Note: For the interrupt acceptance timing, see table 4.1, Exception Source Detection and
interrupt exception handling)
Usage Notes
Interrupt service routine—
Exception Handling Start Timing, in section 4.1.2, Exception Handling Operation.
Figure 5.4 Example of Pipelining in IRQ Interrupt Acceptance
…… (a)
first instruction
Overrun fetch
When m1 = m2 = m3, the interrupt response time is 11 cycles.
IRQ
IRQOUT
Instruction fetched from memory where program is stored.
The fetched instruction is decoded.
Data operations and address calculations are performed
according to the decoded results.
Data in memory is accessed.
Interrupt accepted
(edge)
(level)
3
F D
F
E E
3
5 + m1 + m2 + m3
…… (b)
m1 m2 1 m3 1
M M E
M E E
F D E