HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 120

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 8.3
Bits 15–8:
RW7–RW0
0
1
Notes: 1. Sampled in the address/data multiplexed I/O space
• Bits 7–2 (reserved): These bits always read as 1. The write value should always be 1.
• Bit 1 (wait state control during write (WW1)): WW1 determines the number of states in write
Note: Write 0 to WW1 only when area 1 is used as DRAM space (DRAME bit of BCR is 1).
Bit 1: WW1
0
1
• Bit 0 (reserved): This bit always reads 1. The write value should always be 1.
100 RENESAS
cycles for the DRAM space (area 1) and whether or not to sample the WAIT signal. When the
DRAM enable bit (DRAME) of the BCR is set to 1 and area 1 is being used as DRAM space,
clearing WW1 to 0 makes the column address output cycle finish in 1 states (short pitch).
When WW1 is set to 1, it finishes in 2 states plus the wait states from the WAIT signal (long
pitch).
2. During a CBR refresh, the WAIT signal is ignored and the wait state from the RLW1
Never write 0 to WW1 when area 1 is used as external memory space (DRAME is 0).
and RLW0 bits of RCR is inserted.
WAIT
Pin Input
Signal
Not
sampled
during
read
cycle*
Sampled
during
read
cycle
(initial
value)
Read Cycle State Description
DRAM Space (DRAME = 1)
Column address cycle: 1 state (short pitch)
Column address cycle: 2 states + wait state
from WAIT (long pitch) (initial value)
1
External Memory
Space
• Areas 1, 3–5,7: 1
state, fixed
Areas 0, 2, 6: 1 state
+ long wait state
Areas 1, 3–5, 7: 2
states + wait states
from WAIT
Areas 0, 2, 6: 1 state
+ long wait state +
wait state from
WAIT
External Memory Space
DRAM Space
Column add-
ress cycle: 1
state, fixed
(short pitch)
Column
address cycle:
2 states + wait
state from
WAIT (long
pitch)*
Read Cycle States
2
Multi-
Plexed
I/O
4 states
+ wait
states
from
WAIT
Area 1's External Memory
Space (DRAME = 0)
Setting inhibited
2 states + wait state from WAIT
On-chip
Peripheral
Module
3 states,
fixed
Internal space
On-chip
ROM and
RAM
1 state,
fixed