HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 43

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

cycles.
T bit: T bit (in the status register) is set according to the result of a comparison, and in turn is the
condition (True/False) that determines if the program will branch. The T bit in the status register is
only changed by selected instructions, thus improving the processing speed.
Table 2.4
CPU of SH7000 Series
CMP/GE R1, R0
BT
BF
ADD
TST
BT
Immediate Data: Byte (8-bit) immediate data is located in the instruction code. Word or long
word immediate data is not located in instruction codes but is stored in a memory table. The
memory table is accessed by a immediate data transfer instruction (MOV) using the PC relative
addressing mode with displacement.
Table 2.5
Classification
8-bit immediate
16-bit immediate
32-bit immediate
Note: The address of the immediate data is accessed by @(disp, PC).
Absolute Address: When data is accessed by absolute address, the value already in the absolute
address is placed in the memory table. By loading the immediate data when the instruction is
executed, that value is transferred to the register and the data is accessed in the indirect register
addressing mode.
20 RENESAS
TRGET0
TRGET1
#–1, R0
R0, R0
TRGET
T bit
Immediate Data Accessing
CPU of SH7000 Series
MOV
MOV.W @(disp,PC), R0
.........
.DATA.W
MOV.L @(disp,PC), R0
.........
.DATA.L
Description
T bit is set when R0
branches to TRGET0 when R0
and to TRGET1 when R0<R1.
T bit is not changed by ADD. T bit is set
when R0=0. The program branches if
R0=0.
#H'12, R0
H'1234
H'12345678
R1. The program
R1
Conventional CPU
MOV.B #H'12, R0
MOV.W #H'1234, R0
MOV.L #H'12345678, R0
Conventional CPU
CMP.W R1, R0
BGE
BLT
SUB.W #1, R0
BEQ
TRGET0
TRGET1
TRGET