HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 201

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Bit 0 (DMA master enable bit (DME)): DME enables or disables DMA transfers on all
Bit 0: DME
0
1
9.3
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto-request, external request, and on-chip
module request. Transfer can be in either the single address mode or the dual address mode. The
bus mode can be either burst or cycle steal
9.3.1
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (TCR), DMA channel control registers (CHCR), and DMA operation
register (DMAOR) are set, the DMAC transfers data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of
3. When the specified number of transfer have been completed (when TCR reaches 0), the
4. When an address error occurs in the DMAC or an NMI interrupt is generated, the transfer is
Figure 9.2 is a flowchart of this procedure.
182 RENESAS
channels. A channel becomes enabled for a DMA transfer when the DE bit in each DMA's
CHCR and the DME bit are set to 1. For this to be effective, however, the TE bit of each
CHCR and the NMIF and AE bits must all be 0. When the DME bit is cleared, all channel
DMA transfers are aborted.
data (for an auto-request, the transfer begins automatically when the DE bit and DME bit are
set to 1. The TCR value will be decremented by 1). The actual transfer flows vary by address
mode and bus mode.
transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent
to the CPU.
aborted. Transfers are also aborted when the DE bit of the CHCR or the DME bit of the
DMAOR are changed to 0.
Operation
DMA Transfer Flow
Description
Disable DMA transfers on all channels (initial value)
Enable DMA transfers on all channels