HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 367
HD6417020SVX12I
Manufacturer Part Number
HD6417020SVX12I
Description
IC SUPERH MPU ROMLESS 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet
1.HD6417020SVX12IV.pdf
(511 pages)
Specifications of HD6417020SVX12I
Core Processor
SH-1
Core Size
32-Bit
Speed
12.5MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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• Bit 2 (transmit-end interrupt enable (TEIE)): TEIE enables or disables the transmit-end
Bit 2: TEIE
0
1
• Bits 1 and 0 (clock enable 1 and 0 (CKE1 and CKE0)): CKE1 and CKE0 select the SCI clock
Bit 1:
CKE1
0
0
1
1
Notes: 1. The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to
RENESAS 350
interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is
transmitted.
source and enable or disable clock output from the SCK pin. Depending on the combination of
CKE1 and CKE0, the SCK pin can be used for general-purpose input/output, serial clock
output, or serial clock input.
The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in the clocked synchronous mode, or when
an external clock source is selected (CKE1 = 1). Select the SCI operating mode in the serial
mode register (SMR) before setting CKE1 and CKE0. For further details on selection of the
SCI clock source, see table 13.9 in section 13.3, Operation.
Bit 0:
CKE0
0
1
0
1
2. Initial value
3. The output clock frequency is the same as the bit rate.
4. The input clock frequency is 16 times the bit rate.
select the SCK function and the SCK input/output of the SCK pin.
Description*
Synchronous mode
Clocked synchronous mode Internal clock, SCK pin used for serial clock output*
Synchronous mode
Clocked synchronous mode Internal clock, SCK pin used for serial clock output
Synchronous mode
Clocked synchronous mode External clock, SCK pin used for serial clock input
Synchronous mode
Clocked synchronous mode External clock, SCK pin used for serial clock input
Description
Transmit-end interrupt (TEI) requests are disabled* (initial value)
The TEI request can be cleared by reading the TDRE bit in the serial
status register (SSR) after it has been set to 1, then clearing TDRE to
0; by clearing the transmit end (TEND) bit to 0; or by clearing the TEIE
bit to 0.
Transmit-end interrupt (TEI) requests are enabled.
1
Internal clock, SCK pin used for input pin (input
signal is ignored or output pin output level is
undefined)
Internal clock, SCK pin used for clock output*
External clock, SCK pin used for clock input*
External clock, SCK pin used for clock input*
4
4
3
2
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