HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 197

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Bit 7 (acknowledge mode bit (AM)): In the dual address mode, AM selects whether the DACK
Bit 7: AM
0
1
• Bit 6 (acknowledge Level Bit (AL)): AL selects active high signal or active low signal for the
Bit 6: AL
0
1
• Bit 5 (DREQ select bit (DS)): DS selects the DREQ input detection method used. This bit is
Bit 5: DS
0
1
• Bit 4 (transfer bus mode bit (TM)): TM selects the bus mode for DMA transfers. The TM bit is
Bit 4: TM
0
1
178 RENESAS
signal is output during the data read cycle or write cycle. This bit is valid only in channels 0
and 1. The AM bit is initialized to 0 by resets or in standby mode. The AM bit is not valid in
single address mode.
DACK signal. This bit is valid only in channels 0 and 1. The AL bit is initialized to 0 by resets
or in standby mode.
valid only in channels 0 and 1. The DS bit is initialized to 0 by resets or in standby mode.
initialized to 0 by resets or in standby mode. When the source of the transfer request is an on-
chip peripheral module, see table 9.4, Selecting On-Chip Peripheral Module Request Modes
with the RS Bit.
Description
DACK is output in read cycle (initial value)
DACK is output in write cycle
Description
DACK is active high (initial value)
DACK is active low
Description
DREQ detected by low level (initial value)
DREQ detected by falling edge
Description
Cycle-steal mode (initial value)
Burst mode