HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 176

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 8.11 Bus Cycle States when Accessing Address Spaces
Address Space
External memory (areas
1, 3–5, 7)
External memory (Areas
0, 2, 6; long wait avail-
able)
DRAM space (area 1)
Multiplexed I/O space
(area 6)
On-chip peripheral mod-
ule space (area 5)
On-chip ROM (area 0)
On-chip RAM (area 7)
Address Space
External memory (areas
1, 3–5, 7)
External memory (Areas
0, 2, 6; long wait
available)
DRAM space (area 1)
Multiplexed I/O space
(area 6)
On-chip peripheral
module space (area 5)
On-chip ROM (area 0)
On-chip RAM (area 7)
Note: The number of long wait states (1 to 4) is set in WCR3.
156 RENESAS
Corresponding Bits in WCR1
and WCR2 = 0
1 state fixed; WAIT signal ignored 2 states + wait states from WAIT
1 state + long wait state*, WAIT
signal ignored
Column address cycle: 1 state,
WAIT signal ignored (short pitch)
4 states + wait states from WAIT signal
3 states fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
WW1 of WCR1 = 0
2 states + wait states from WAIT signal
1 state + long wait state*
Column address cycle: 1 state,
WAIT signal ignored (short pitch)
4 states + wait states from WAIT signal
3 states fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
1 state fixed, WAIT signal ignored
CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC Single
CPU Write Cycle, DMAC Dual Mode Memory Write Cycle
Mode Memory Read/Write Cycle
+
wait states from WAIT signal
Corresponding Bits in WCR1
and WCR2 = 1
signal
1 state + long wait state*
states from WAIT signal
Column address cycle: 2 states +
wait states from WAIT signal
(long pitch)
WW1 of WCR1 =1
Column address cycle: 2 states +
wait states from WAIT signal
(long pitch)
+
wait