HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 126

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Bit 12 (burst operation enable (BE)): BE selects whether or not to perform burst operation, a
Bit 12: BE
0
1
• Bit 11 (CAS duty (CDTY)): CDTY selects 35% or 50% of the T
Bit 11: CDTY
0
1
• Bit 10 (multiplex enable bit (MXE)): MXE determines whether or not DRAM row and column
Bit 10: MXE
0
1
• Bits 9 and 8 (multiplex shift count 1 and 0 (MXC1 and MXC0)): Shift row addresses
106 RENESAS
high speed page mode. When burst operation is not selected (0), the row address is not
compared but instead is transferred to the DRAM every time and full access is performed.
When burst operation is selected (1), row addresses are compared and burst operation with the
same row address as the previous is performed (in this access, no row address is output and the
column address and CAS signal alone are output).
ratio of the signal CAS in the short-pitch access. When cleared to 0, the CAS signal high level
duty is 50%; when set to 1, it is 35%. Only set to 1 when the operating frequency is a
minimum of 10 MHz.
addresses are multiplexed. When cleared to 0, addresses are not multiplexed; when set to 1,
they are multiplexed.
downward by a certain number of bits (8–10) when row and column addresses are multiplexed
(MXE = 1). Regardless of the MXE bit setting, these bits also select the range of row addresses
compared in burst operation.
Description
Normal mode: full access (initial value)
Burst operation: high-speed page mode
Description
CAS signal high level duty cycle is 50% of the T
CAS signal high level duty cycle is 35% of the T
Description
Multiplex of row and column addresses disabled (initial value)
Multiplex of row and column addresses enabled
C
state as the high-level duty
C
C
state (initial value)
state