HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 337

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Five-Phase Pulse Output (figure 11.5):
1. Set the GRA of the ITU that serves as output trigger as the output compare register. Set the
2. Write H'FFC0 in the PBCR1, write H'F8 in the NDERB, and set G3CMS0, G3CMS1,
3. When the selected ITU channel starts operating and a compare-match occurs, the values in the
4. Five-phase pulse output can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08,
H'0000
cycle time in the GRA of the ITU and select to clear the counter upon compare match A. Set
the IMIEA bit of TIER to 1 to enable the compare match A interrupt.
G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the
output trigger. Write output data H'80 in the NDRB.
NDRB are transferred to the PBDR and output. The compare-match/input capture A (IMIA)
interrupt service routine writes the next output data (H'C0) in the NDRB.
H'88… at successive compare-match interrupts. If the DMA controller is set for activation by
compare-match, pulse output can be obtained without loading the CPU.
NDRB
PBDR
TP15
TP14
TP13
TP12
TP11
GRA
TCNT
value TCNT
80
8000 C000 4000 6000 2000 3000 1000 1800 0800 8800 8000 C000
Figure 11.5 TPC Output Example (5-Phase Pulse Output)
C0
40
60
Compare matches
20
30
10
18
08
88
80
C0
RENESAS 319
Time