HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 313

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.6.13 Clearing the Complementary PWM Mode
Figure 10.69 shows the procedure for clearing the complementary PWM mode. First, reset the
combination mode bits CMD1 and CMD0 in the timer function control register (TFCR) from 10 to
either 00 or 01. The mode will switch from complementary PWM mode to normal operating
mode. Next, wait for at least 1 clock of the counter input clock being used for channels 3 and 4
and then clear the counter start bits STR3 and STR4 of the timer start register (TSTR). The
channels 3 and 4 counters TCNT3 and TCNT4 will stop counting. Clearing the complementary
PWM mode by any other procedure may result in changes other than those set for the output
waveform when complementary PWM mode is set again.
10.6.14 ITU Operating Modes
Tables 10.18–10.22 show the ITU operating modes for channels 0–4.
10.6.15 Note on Counter Clearing by Input Capture
If TCNT is cleared (to H'0000) by input capture when its value is H'FFFF, overflow will not
occur.
Complementary PWM mode
Clear complementary
Normal operation
PWM mode
Halt Count
Figure 10.69 Clearing the Complementary PWM Mode
1. Clear the CMD1 bit of the TFCR to 0
2. Wait at least 1 clock after setting channels 3 and 4
to set channels 3 and 4 for normal operation
for normal operation and then clear the STR3 and
STR4 bits of the TSTR to 0 to halt the TCNT3 and
TCNT4 counters
RENESAS 295