HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 199

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Bit 0 (DMA enable bit (DE)): DE enables or disables DMA transfers. In the auto-request
Bit 0: DE
0
1
9.2.5
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset or the
standby mode.
Note: Write only 0 to clear the flag.
• Bits 15–10 (reserved): These bits always read 0. The write value should always be 0.
180 RENESAS
mode, the transfer starts when this bit or the DME bit of the DMAOR is set to 1. The TE bit
and the NMIF and AE bits of the DMAOR must be all cleared to 0. In external request mode
or on-chip peripheral module request mode, the transfer begins when the DMA transfer request
is received from said device or on-chip peripheral module, provided this bit and the DME bit
are set to 1. As with the auto request mode, the TE bit and the NMIF and AE bits of the
DMAOR must be all cleared to 0. The transfer can be stopped by clearing this bit to 0.
The DE bit is initialized to 0 by resets or in standby mode.
Initial value:
Initial value:
Bit name:
Bit name:
DMA Operation Register (DMAOR)
R/W:
R/W:
Bit:
Bit:
——
15
—
0
R
7
0
R
Description
DMA transfer disabled (initial value)
DMA transfer enabled
14
—
—
0
R
6
0
R
13
—
—
0
R
5
0
R
12
—
—
0
R
4
0
R
11
—
—
0
R
3
0
R
R/(W)*
AE
10
—
0
R
2
0
R/(W)*
NMIF
PR1
R/W
9
0
1
0
DME
PR0
R/W
8
0
0
0
R