HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 330

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Bits 7–0 (next data enable 7–0 (NDER7–NDER0)): NDER7–NDER0 select enable/disable for
Bit 7–0: NDER7–NDER0 Description
0
1
11.2.6
NDERB is an eight-bit read/write register that enables TPC output groups 3 and 2 (TP15–TP8) on
a bit-by-bit basis.
When the bits enabled for TPC output by NDERB generate the ITU compare match selected in the
TPC output control register, the value of the next data register B (NDRB) is automatically
transferred to the corresponding PBDR bits and the output value is updated. For disabled bits,
there is no transfer and the output value does not change. When reset, NDERB is initialized to
H'00. It is not initialized by standby mode.
• Bits 7–0 (next data enable 15–8 (NDER15–NDER8)): NDER15–NDER8 select enable/disable
Bit 7–0:
NDER15–NDER8
0
1
312 RENESAS
TPC output groups 1 and 0 (TP7–TP0) in bit units.
for TPC output groups 3 and 2 (TP15–TP8) in bit units.
Initial value:
Initial value:
Bit name:
Bit name: NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
Next Data Enable Register B (NDERB)
R/W:
R/W:
Bit:
Bit:
NDER7
R/W
R/W
7
0
7
0
Disables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7–
PB0 is disabled) (initial value)
Enables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7–
PB0 is enabled)
Description
Disables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to
PB15–PB8 is disabled) (initial value)
Enables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to
PB15–PB8 is enabled)
NDER6 NDER5
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
NDER4 NDER3
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
NDER2
R/W
R/W
2
0
2
0
NDER1 NDER0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0