HD6417020SVX12I Renesas Electronics America, HD6417020SVX12I Datasheet - Page 26

• Manufacturer Part Number: HD6417020SVX12I
• Description: IC SUPERH MPU ROMLESS 100TQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SVX12I

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 12.5MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 1.1
Feature
Interrupt controller (INTC)
User break controller (UBC)
Clock pulse generator (CPG)
Bus state controller (BSC)
Features of the SH7020 and SH7021 Microcomputers (cont)
Description
Nine external interrupt pins (NMI, IRQ0–IRQ7)
Thirty internal interrupt sources
Sixteen programmable priority levels
Generates an interrupt when the CPU or DMAC generates a bus
cycle with specified conditions
Simplifies configuration of a self-debugger
On-chip clock pulse generator (maximum operating frequency:
20 MHz):
• 20-MHz pulses can be generated from a 20-MHz crystal with a
Supports external memory access:
• Sixteen-bit external data bus
Address space divided into eight areas with the following preset
features:
• Bus size (8 or 16 bits)
• Number of wait cycles can be defined by user.
• Type of area (external memory area, DRAM area, etc.)
• When the DRAM area is accessed:
• Chip select signals (CS0 to CS7) are output for each area
DRAM refresh function:
• Programmable refresh interval
• Supports CAS-before-RAS refresh and self-refresh modes
DRAM burst access function:
• Supports high-speed access modes for DRAM
Wait cycles can be inserted by an external WAIT signal
One-stage write buffer improves the system performance
Data bus parity can be generated and checked
duty cycle correcting circuit
— Simplifies connection to ROM, SRAM, DRAM, and
— RAS and CAS signals for DRAM are output
— Tp cycles can be generated to assure RAS precharge
— Address multiplexing is supported internally, so DRAM
peripheral I/O
time
can be connected directly
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