UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 927

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.4 Cautions for Power-on-Clear Circuit
voltage (V
from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following
action.
Note 1
In a system where the supply voltage (V
<Action>
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Notes 1.
Remark n = 00 to 11
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
POR
2.
, V
If reset is generated again during this period, initialization processing <2> is not started.
A flowchart is shown on the next page.
No
PDR
), the system may be repeatedly reset and released from the reset status. In this case, the time
Figure 20-3. Example of Software Processing After Reset Release (1/2)
Setting timer array unit
(to measure 50 ms)
50 ms has passed?
processing <1>
processing <2>
Clearing WDT
(TMIFn = 1?)
Initialization
Initialization
Reset
Yes
Power-on-clear
CHAPTER 20 POWER-ON-CLEAR CIRCUIT
DD
User’s Manual U19678EJ1V1UD
) fluctuates for a certain period in the vicinity of the POC detection
;
; f
; Initial setting for port.
Check the reset source, etc.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Source: f
Timer starts (TSn = 1).
CLK
= Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default)
where comparison value = 102: ≅ 50 ms
CLK
(8.4 MHz (MAX.))/2
Note 2
12
,
925