UPD78F1203MC-CAB-AX Renesas Electronics America, UPD78F1203MC-CAB-AX Datasheet - Page 580

• Manufacturer Part Number: UPD78F1203MC-CAB-AX
• Description: MCU 16BIT 78K0R/LX3 30-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Ix3r

Specifications of UPD78F1203MC-CAB-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.3 Registers Used in A/D Converter
(1) Peripheral enable register 0 (PER0)
578
Address: F00F0H
The A/D converter uses the following eight registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D converter mode register 1 (ADM1)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode registers 2, 8, 15 (PM2, PM8, PM15)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
Symbol
PER0
PER0 is used to enable or disable supplying the clock to the peripheral hardware macro. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Cautions 1. When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to a
Notes 1. RTCEN bit is not provided in the 78K0R/IB3. In the 78K0R/IB3, bit 7 of PER0 register is fixed
RTCEN
ADCEN
2. Be sure to clear bits 0, 1, 3, and 6 (78K0R/IB3: 0, 1, 3, 4, 6, 7, 38-pin and 44-pin products of
<7>
0
1
After reset: 00H
2. IICAEN bit is not provided in the 78K0R/IB3 and the 38-pin and 44 pin products of the
control register of the A/D converter is ignored, and, even if the register is read, only the
default value is read (except for port mode registers 2, 8, 15 (PM2, PM8, PM15)).
the 78K0R/IC3: 0, 1, 3, 4 and 6) of PER0 register to 0.
Note 1
to 0.
78K0R/IC3. In the 78K0R/IB3 and the 38-pin and 44 pin products of the 78K0R/IC3, bit4 of
PER0 register is fixed to 0.
Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
Enables input clock supply.
• SFR used by the A/D converter can be read/written.
Figure 12-2. Format of Peripheral Enable Register 0 (PER0)
6
0
R/W
ADCEN
CHAPTER 12 A/D CONVERTER
<5>
User’s Manual U19678EJ1V1UD
IICAEN
Control of A/D converter input clock
<4>
Note 2
3
0
SAU0EN
<2>
1
0
0
0